here is the 1995 paper that the #Spectre paper published in 2019 cites - and don't forget the research was funded by the NSA:
An in-depth analysis of the 80x86 processor families identifies architectural properties that may have unexpected, and undesirable, results in secure computer systems. In addition, reported implementation errors in some processor versions render them undesirable for secure systems because of potential security and reliability problems. In this paper, we discuss the imbalance in scrutiny for hardware protection mechanisms relative to software, and why this imbalance is increasingly difficult to justify as hardware complexity increases. We illustrate this difficulty with examples of architectural subtleties and reported implementation errors.
citeseerx.ist.psu.edu/viewdoc/β¦
Sibert, O., Porras, P. A., & Lindell, R. (1995, May). The intel 80x86 processor architecture: pitfalls for secure systems. In Proceedings 1995 IEEE Symposium on Security and Privacy (pp. 211-222). IEEE.
Haelwenn /ΡΠ»Π²ΡΠ½/
in reply to theruran ππ΄ • • •Nate Cull (.social)
in reply to Haelwenn /ΡΠ»Π²ΡΠ½/ • • •theruran ππ΄
in reply to theruran ππ΄ • • •Vertigo #$FF
in reply to theruran ππ΄ • • •Kartik Agaram
in reply to Vertigo #$FF • • •Vertigo #$FF
in reply to Kartik Agaram • • •Neither does x86 or POWER.
Most RISC-V processors have branch prediction.
And the issue isn't even branch prediction. The issue is predicting branches across a privilege boundary. Which most processors do because the ability to predict when you're going to make a system call helps amortize the cost of making a kernel call.
Zack Weinberg
in reply to Kartik Agaram • • •Zack Weinberg
in reply to Zack Weinberg • • •Kartik Agaram
in reply to Zack Weinberg • • •Computers are a million times faster than 20 years ago. I'll take 250,000 times faster?
To clarify my original comment, I was asking only about RISC-V processors.
Zack Weinberg
in reply to Kartik Agaram • • •Zack Weinberg
in reply to Zack Weinberg • • •Hmm, lemme be more specific. Not having a branch predictor is not a big deal as long as your CPU core is both βin-orderβ and βsingle issueβ. The performance hit in that case is 4*(fraction of instructions executed that are conditional branches), and conditional branches are usually about a tenth of all instructions, so you can see that this is livable.
In-order single issue is the design used for microcontrollers (because itβs small and power efficient) and research designs where speed isnβt the subject of the research (because itβs way less Verilog to write).
Zack Weinberg
in reply to Zack Weinberg • • •Zack Weinberg
in reply to Zack Weinberg • • •Zack Weinberg
in reply to Zack Weinberg • • •Seirdy
in reply to Vertigo #$FF • • •The right thing for the wrong reasons: FLOSS doesn't imply security
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